Low Power Code Generation for a RISC Processor by Register Pipelining
نویسندگان
چکیده
This paper presents the implementation of the compiler technique register pipelining with respect to energy optimization and its comparison against performance optimization. Generally, programs optimized for performance are also energy optimized. An exception to this rule is shown where the use of register pipelining improves the energy consumption by 17% while bringing down performance by 8.8%. Therefore, a detailed consideration of energy consumption within the processor and the memories is necessary.
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